1. Field of the Invention
This invention generally relates to a ball grid array (BGA) package, and more particularly to a BGA package using wire-bonding technique.
2. Description of the Related Art
As electronic devices have become more smaller and thinner, the velocity and the complexity of IC chip become more and more higher. Accordingly, a need has arisen for higher package efficiency. To meet the need, the ball grid array (BGA) technology has been developed by the semiconductor industry.
Although the conductive traces pads on a BGA substrate can be lithographically defined to achieve a very fine pitch, the bond pad pitch on the semiconductor die is typically restricted from achieving a comparable pitch due to spacing and design rules used to account for wire bonding methods and tolerances, such as capillary tool interference during wire bonding.
Conventional IC bond pad designs include (a) single in-line bond pad design and (b) staggered bond pad design. Typically, the number of connections to external circuit elements, commonly referred to as “input-output” or “I/O” connections, is determined by the structure and function of the chip. Advanced chips capable of performing numerous functions may require substantial number of I/O connections. For high I/O count IC chips, the staggered bond pad design have been used so as to increase the maximum allowable pad number that can be designed on a chip. This has the benefit of providing not only more bonding pads per chip but also shorter metal wires and thus faster circuits.
FIG. 1 depicts a conventional plastic ball grid array (PBGA) package 100 comprising a chip 110 with a staggered bond pad design disposed on the upper surface of a substrate 120. The upper surface of the substrate 120 is provided with a ground ring 122, a power ring 124, and a plurality of conductive traces 126 (see FIG. 2). The active surface of the chip 110 is provided with a plurality of bonding pads 112 positioned in two rows. The bonding pads 112 on the chip 110 typically include power supply pads, ground pads and I/O pads. The power supply pads are used for supplying the source voltage. The ground pads are used for supplying the ground potential.
Typically, the number of the I/O pads accounts for about two thirds of the total number of the bonding pads 112. Thus, at least some of the outer row of bonding pads 112 must be designed as I/O pads. The outer row of bonding pads 112 is referred to as bonding pads closest to the sides of the chip. Therefore, at least four tiers of bonding wires with different loop heights are required for avoiding short circuiting wherein the bonding wires electrically connect the chip 110 to the substrate 120. The first tier bonding wires 112a (lowest loop height) connect the ground pads designed in the outer row of the bonding pads to the ground ring 122 of the substrate 120. The second tier bonding wires 112b connect the power supply pads designed in the outer row of the bonding pads to the power ring 124 of the substrate 120. The third tier bonding wires 112c connect the I/O pads designed in the outer row of the bonding pads to corresponding conductive traces 126 of the substrate 120. The fourth tier bonding wires 112d (which has a highest loop height) connect the I/O pads designed in the inner row of the bonding pads to corresponding conductive traces 126 of the substrate 120. The wire bonding parameters of each tier must be optimized individually. Therefore, the four tiers of bonding wires 112a, 112b, 112c and 112d require at least four times of wire bonding operation. Difficulty and risks of wire bonding are proportional to the times of wire bonding operation required.
Taiwan patent application No.89101235 filed by the present applicant on Jan. 24, 2000 (U.S. counterpart patent application Ser. No. 09/534,984 filed on Mar. 27, 2000), which is incorporated herein by reference, discloses a BGA package having a chip disposed on the upper surface of a substrate. The chip has a plurality of bonding pads located about the periphery thereof. The bonding pads of the chip are positioned in three rows, an inner row, a middle row, and an outer row along the sides of the chip. Only power supply pads and ground pads are designed in the outer row of bonding pads. The BGA package further includes three sets of bonding wires, wherein a first set of bonding wires electrically connect the power supply pads and ground pads on the chip to the power ring and the ground ring on the substrate respectively, a second set of bonding wires electrically connect the middle row of the bonding pads to the corresponding conductive traces on the substrate, and the third set of bonding wires electrically connect the inner row of the bonding pads to the corresponding conductive traces on the substrate. The three sets of bonding pads respectively have the same loop height. However, the patent also failed to provide a proper arrangement of the bonding pads to meet the requirement of the chip with high I/O pads.
Accordingly, there exist needs for provide a BGA package having a suitable arrangement of the bonding pads to meet requirement of the chip with high I/O pads and having the reduced loop height of the bonding wires.